The present invention relates to a non-volatile memory device, and more particularly, to triple self-alignment of gates within such a device.
An electrically erasable programmable memory (EEPROM) cell is a non-volatile writable and erasable memory cell that requires very low operating currents. The unit cell of an EEPROM may be formed by connecting a memory transistor in series with a select transistor. Some EEPROM designs are integrated so that the features of the two transistors are merged. Flash memories describe a family of single-transistor cell EEPROMs. Cell sizes of flash memory are about half that of a two-transistor EEPROM.
Flash memory designs differ in their cell structure based on whether they require one or several transistors per cell. A split-gate flash cell provides the equivalent of a two-transistor architecture, but requires only slightly more semiconductor real estate than a single transistor cell. Flash memory cells may include a floating storage gate interposed between a select gate and the area of the silicon substrate that is the channel of the memory cell transistor. Erasing, writing, or reading of such a cell involves injecting or removing electrons to or from the floating gate. Applying different combinations of voltages on its control gate, source, drain, and substrate controls this erasing, writing and reading of the cell.
For a split-gate flash memory to operate properly, it may be necessary for the select gate to at least cover the distance between the drain region (or source region) and the floating gate. If this distance is not constant, the length of the select gate may need to overcompensate for the variance in distance to ensure that the split-gate flash memory operates properly. Furthermore due to the overcompensation in the select gate length, a non-self-aligned split gate process deters cell size scaling. Moreover, cell characteristics,. such as program efficiency and cell current, are severely affected by misalignment, which may occur in a non-self-aligned gate process.
In one aspect, the present invention describes a method for fabricating a triple self-aligned non-volatile memory device. The method includes forming isolation oxide on a substrate. A plurality of floating gates are formed by depositing and self-aligning a first polysilicon layer to the isolation oxide. A common source area is then defined on the substrate between the floating gates. A second polysilicon layer is deposited over the common source area and self-aligned with respect to the isolation oxide. A third polysilicon layer is deposited adjacent to the plurality of floating gates. A plurality of select gates are then formed by self-aligning the third polysilicon layer to the isolation oxide. Furthermore, at least one drain area is defined on the substrate.
In another aspect, the invention describes a triple self-aligned non-volatile memory device. The device includes an isolation oxide, a plurality of floating gates, a common source area, a plurality of select gates, and a contact. The floating gates, having a first polysilicon layer, are self-aligned to the isolation oxide. A second polysilicon layer is formed on top of the common source area between the floating gates. The second polysilicon layer is also self-aligned to the isolation oxide. The select gates are provided adjacent to the floating gates. Further, the select gates are self-aligned to the isolation oxide. A contact provides connection to a drain region.